Memory Solution Research Intern
Published:
- Mentor: Caroline Kahn
- Characterize the performance of Samsung’s CXL-based memory devices and develop innovative memory solutions and modeling approaches for AI/ML workloads.
Work Experience
Processor Architecture Research Intern
Published:
- Mentors: Shankar Balachandran, Anant V. Nori, Sreenivas Subramoney
- Designed a framework for tensor tracking in GenAI workloads for architectural exploration on Xeon Processors.
Front-end Design Verification Engineer
Published:
- Verified SoC integration of registers, communication peripherals, and co-processors for C2000 real-time microcontrollers.
- Handled critical silicon debugs for functional test patterns on Automatic Test Equipment (ATE).
- Developed a Perl-based automation framework to auto-generate RTL for memory-mapped registers and the verification test cases, significantly reducing manual efforts and errors by 80%.
Research Project Intern
Published:
- Advisor: Prof. Tohru Ishihara, Graduate School of Informatics
- Proposed a real-time Minimum Energy Point (MEP) tracking method by analyzing power consumption on RISC-V-based PULPino processor, achieving at most 3.1% energy loss.
Research Project — Scale-free Hyperbolic CORDIC Architecture
Published:
- Advisor: Prof. Bishnu P Das, ECE Department
- Designed a low-latency CORDIC architecture to compute sinh and cosh functions with desired precision using a novel power-of-2 coefficient Taylor series approximation.
- Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023.
Front-end Design Verification Intern
Published:
- Worked with C2000 RTL team to automate RTL generation for various memory-mapped register IPs.
Research Project Intern — Image Processing based Fish Seed Counting
Published:
- Advisor: Prof. Maryam S. Baghini, VLSI Design Lab
- Proposed a novel data-acquisition apparatus to create a training dataset for a crowd-counting-based CNN model for fish seed counting.