Khyati Kiyawat(she/her)

Khyati Kiyawat(she/her)

Ph.D. Student, Department of Computer Science, University of Virginia

Posts by Collection

portfolio

publications

Real-time minimum energy point tracking using a predetermined optimal voltage setting strategy

Published in ISVLSI, 2020

A real-time minimum energy point (MEP) tracking method based on a predetermined, per-chip linear MEP-curve model, avoiding costly runtime power measurement.

Recommended citation: K. Kiyawat, Y. Masuda, J. Shiomi and T. Ishihara, "Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy", 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 415-421, 2020. https://ieeexplore.ieee.org/document/9155057

An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation

Published in IEEE TVLSI, 2023

A scaling-free hyperbolic CORDIC design using a novel low-complexity power-of-2 Taylor series approximation, cutting latency, area, and power versus prior designs, with silicon validation in TSMC 180nm.

Recommended citation: A. Verma, K. Kiyawat, B. P. Das and P. K. Meher, "An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 8, pp. 1167-1177, Aug. 2023. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10161702

Architectural Modeling and Benchmarking for Digital DRAM PIM

Published in IISWC 2024, 2024

A framework for architectural modeling and benchmarking of digital DRAM processing-in-memory architectures.

Recommended citation: F. Siddique, D. Guo, Z. Fan, M. Gholamrezaei, M. Baradaran, A. Ahmed, H. Abbot, K. Durrer, K. Nandagopal, E. Ermovick, K. Kiyawat, B. Gul, A. Mughrabi, A. Venkat, K. Skadron. "Architectural Modeling and Benchmarking for Digital DRAM PIM." IISWC, 2024. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10763591

Membrane: Accelerating Database Analytics with DRAM-Based PIM Filtering and Schema Denormalization

Published in ACM TACO 2025, 2025

A system that accelerates database analytics by combining DRAM-based PIM filtering with schema denormalization.

Recommended citation: Akhil Shekar, Kevin Gaffney, Martin Prammer, Khyati Kiyawat, Lingxi Wu, Helena Caminal, Zhenxing Fan, Yimin Gao, Ashish Venkat, José F. Martínez, Jignesh Patel, Kevin Skadron. "Membrane: Accelerating Database Analytics with DRAM-Based PIM Filtering and Schema Denormalization." ACM TACO, 2025. https://arxiv.org/abs/2504.06473

Sangam: A Chiplet-Based DRAM-PIM Accelerator with CXL Integration for LLM Inferencing

Published in arXiv, 2025

A chiplet-based DRAM processing-in-memory accelerator with CXL integration designed for efficient LLM inference.

Recommended citation: Khyati Kiyawat, Zhenxing Fan, Yasas Seneviratne, Morteza Baradaran, Akhil Shekar, Zihan Xia, Mingu Kang, Kevin Skadron. "Sangam: A Chiplet-Based DRAM-PIM Accelerator with CXL Integration for LLM Inferencing." arXiv, Nov 2025. https://arxiv.org/abs/2511.12286

talks

teaching

Graduate Teaching Assistant — CS 2130

Graduate Teaching Assistant, University of Virginia, Department of Computer Science, 2023

Graduate Teaching Assistant for Computer Systems and Organization I (CS 2130), Fall 2023.

Recommended citation: Computer Systems and Organization I (CS 2130), Fall 2023

Graduate Teaching Assistant — CS 3130

Graduate Teaching Assistant, University of Virginia, Department of Computer Science, 2024

Graduate Teaching Assistant for Computer Systems and Organization II (CS 3130), Spring 2024.

Recommended citation: Computer Systems and Organization II (CS 3130), Spring 2024

Graduate Teaching Assistant — CS 6501

Graduate Teaching Assistant, University of Virginia, Department of Computer Science, 2025

Graduate Teaching Assistant for CPU/GPU Memory Systems (CS 6501 Special Topics), Spring 2025.

Recommended citation: CPU/GPU Memory Systems (CS 6501 Special Topics), Spring 2025

Graduate Teaching Assistant — CS 6501

Graduate Teaching Assistant, University of Virginia, Department of Computer Science, 2026

Graduate Teaching Assistant for CPU/GPU Memory Systems (CS 6501 Special Topics), Spring 2026.

Recommended citation: CPU/GPU Memory Systems (CS 6501 Special Topics), Spring 2026

work_exp

Research Project — Scale-free Hyperbolic CORDIC Architecture

Published:

  • Advisor: Prof. Bishnu P Das, ECE Department
  • Designed a low-latency CORDIC architecture to compute sinh and cosh functions with desired precision using a novel power-of-2 coefficient Taylor series approximation.
  • Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023.

Research Project Intern

Published:

  • Advisor: Prof. Tohru Ishihara, Graduate School of Informatics
  • Proposed a real-time Minimum Energy Point (MEP) tracking method by analyzing power consumption on RISC-V-based PULPino processor, achieving at most 3.1% energy loss.

Front-end Design Verification Engineer

Published:

  • Verified SoC integration of registers, communication peripherals, and co-processors for C2000 real-time microcontrollers.
  • Handled critical silicon debugs for functional test patterns on Automatic Test Equipment (ATE).
  • Developed a Perl-based automation framework to auto-generate RTL for memory-mapped registers and the verification test cases, significantly reducing manual efforts and errors by 80%.

Processor Architecture Research Intern

Published:

  • Mentors: Shankar Balachandran, Anant V. Nori, Sreenivas Subramoney
  • Designed a framework for tensor tracking in GenAI workloads for architectural exploration on Xeon Processors.

Memory Solution Research Intern

Published:

  • Mentor: Caroline Kahn
  • Characterize the performance of Samsung’s CXL-based memory devices and develop innovative memory solutions and modeling approaches for AI/ML workloads.