I am a PhD student advised by Prof. Kevin Skadron at the Computer Science Department, University of Virginia. My research focuses on acceleration using intelligent memory systems, and enabling the adoption of Processing in memory (PIM) architectures.

You can find my resume here

Education

• B.Tech., Electronics & Communication Engineering, Indian Institute of Technology (IIT) Roorkee, 2020
• Ph.D in Computer Architecture, University of Virginia, 2027 (expected)

Work experience

• Processor Architecture Research Lab, Intel labs, India
  • I worked with Shankar Balachandran, Anant V. Nori, Sreenivas Subramoney on GenAI workload instrumention and characterizing framework
  • May 2024 - Jan 2025
• Digital Design Engineer, Texas Instruments, India
  • I was part of the Design Verification team for C2000 (high-end industry and automotive) microcontrollers
  • Jul 2020 - Jul 2022
• Research Project Intern, Nagoya University, Japan
  • I was advised by Prof. Tohru Ishihara to work on Power Optimization techniques on RISC-V Pulpino processors
  • Dec 2019 - Feb 2020
• Digital Design Engineer, Texas Instruments, India
  • I worked with C2000 RTL team to automate RTL generation for various memory-mapped register IPs
  • April 2019 - Jul 2019
• Research Project Intern, IIT Bombay, India
  • I was advised by Prof. Maryam S. Baghini to develop a prototype for object sensing using CNN
  • April 2018 - Jun 2018

Publications

Real-time minimum energy point tracking using a predetermined optimal voltage setting strategy

K. Kiyawat, Y. Masuda, J. Shiomi and T. Ishihara, "Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy", 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 415-421, 2020.

An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation

A. Verma, K. Kiyawat, B. P. Das and P. K. Meher, "An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 8, pp. 1167-1177, Aug. 2023.

Talks

Open-Source Processing-in-Memory (PiM) Architecture Design through FPGA Emulation: A Case Study Modeling Sieve

June 18, 2023

Presentation at Open-Source Computer Architecture Research Workshop at ISCA, 2023, Orlando, Florida

Service and leadership

• Co-organizing Systems-Interest-Group meetings to facilitate collaboration and discussions spanning across systems research at the University of Virginia.